(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices and, more particularly, to a method of etching the spacers of the CMOS gate electrode that is used in image sensor devices.
(2) Description of the Prior Art
The manufacturing of semiconductor devices requires the creation of a variety of components that collectively perform functions of data manipulation (logic functions) and of data retention (storage functions). The vast majority of these functions operates in a digital or one-off mode and as such recognize zero and one conditions within the operational levels of the circuits. There are, in addition, applications that make use of analog levels of voltage where the voltage may have a spectrum of values between a high limit and a low limit. There are furthermore applications where both the digital and the analog methods of signal processing reside side by side in the same semiconductor device.
This mixture of functions and processing capabilities brings with it a mixture of components that can coexist within one semiconductor device. Where the vast majority of device components is made up of transistors, gate electrodes and a variety of switching components that address logic processing functions, it is not uncommon to also see resistors and capacitors that form part of a semiconductor device. It is for instance known that capacitors form a basic component of many analog circuits that are used for analog applications such as switched capacitor filters. It is also well known in the art that capacitors are widely applied in digital applications such as the storage node for Dynamic Random Access Memory (DRAM) circuits. This ability of capacitors to function in either the digital or the analog mode is referred to as the mixed mode application of the capacitor.
The DRAM technology is widely used for data storage where one transistor and one capacitor form one DRAM cell. For the capacitor a stacked capacitor is frequently used since this structure has good data storage performance characteristics. To fabricate this device, a modified CMOS process is typically used. One other application in which the CMOS structure has been successfully applied is in the creation of image sensors; it is this latter application that is addressed by the invention.
An image sensor is, in its broadest terms, used to convert an optical image that is focused on the sensor into electrical signals. The image sensor typically includes an array of light detecting elements, where each element produces a signal corresponding to the intensity of light impinging on that element when an image is focused on the array. These signals may then be used, for example, to display a corresponding image on a monitor or may otherwise be used to provide information about the optical image.
One very common type of image sensor is a charge-coupled device (CCD). Integrated circuit chips containing CCD image sensors have a relatively low yield and are expensive due to the specialized processing involved. The CCD's also consume a relatively large amount of power.
A much less expensive type of image sensor can be formed as an integrated circuit by using a CMOS process. In such a CMOS type image sensor, a photodiode or phototransistor (or any other suitable device) is used as the light-detecting element, where the conductivity of the element corresponds to the intensity of light impinging on the element. The variable signal thus generated by the light detecting element is an analog signal whose magnitude is approximately proportional (within a certain range) to the amount of light that impinges on the element.
The light-detecting elements are typically formed in a two-dimensional core array, which is addressable by row and column. Once a row of elements has been addressed, the analog signals from each of the light detecting elements in the row are coupled to the respective columns in the array. An analog-to-digital converter may then be used to convert the analog signals of the columns to digital signals so as to provide only digital signals at the output of the image sensor chip.
What is needed is an inexpensive, but highly efficient, image sensor, which produces reliable images. Implied in this is that leakage current in the spacer regions, that is the source/drain regions of the CMOS gate electrode of the image sensor, is reduced to a minimum. Potential plasma damage that can be caused during the spacer etching must therefore be kept at a minimum.
FIG. 1 shows a Prior Art gate electrode with the etching of the spacer, as follows:
FIG. 1a shows the poly silicon gate electrode 10, a layer 12 of tetra-ethyl-ortho-silicate (TEOS) has been deposited over the gate electrode 10 and the top surface of substrate 14. FIG. 1a shows that only one layer of the dielectric TEOS is deposited in order to form the gate electrode spacers.
FIG. 1b shows the results of the spacer etch, gate electrode spacers 16 are formed after etching has been completed. It is apparent from FIG. 1b that lack in control of the etching or over-etching can readily cause damage the surface areas 18 of substrate 14.
Using current fabrication technology, it is well known that defects in the substrate cause leakage current between the gate electrodes of the image sensor, especially where the substrate defects are caused by plasma damage. It is therefore of key importance to produce a substrate surface that is free of damage and, more particularly, to be able to perform spacer etching without causing damage to the substrate surface. Current practice uses a single layer of dielectric above the spacer between the gate electrodes of the image sensor. With only a single layer of dielectric, it is difficult to sense and control the etch stop above the substrate. This difficulty in controlling the etching process results in substrate surface damage; this in turn results in leakage current between the gate electrodes of the CMOS image sensor device.
An additional problem is that, during the growth of field oxide, a phenomenon occurs that causes defects when the gate oxide is grown. This problem is referred to as white ribbon or white pixels. A thin layer of silicon nitride can form on the silicon surface (i.e., the pad-oxide/silicon surface interface) as a result of the reaction of NH.sub.3 and silicon at that interface. When the gate oxide is grown, the growth rate becomes impeded at the locations where the silicon nitride has been formed. The gate oxide is thus thinner at these locations than elsewhere, causing low-voltage breakdown of the gate oxide.
The invention teaches a new method of etching the spacers for gate electrode structures. Typical silicon oxide gate spacers are formed via anisotropic RIE of a deposited layer of silicon oxide layer, using CHF.sub.3 or CF.sub.4 --O.sub.2 --He as an etchant. Typical silicon nitride spacers are formed via anisotropic RIE of a deposited layer of silicon nitride layer, using CHF.sub.3 or SF.sub.6 --O.sub.2 as an etchant. Typical gate spacers can also be formed using thermal S.sub.i N or using CVD S.sub.i N or using thermal SiO.sub.x N.sub.y or using CVD SiO.sub.x N.sub.y to a thickness within the range between 250 and 1500 Angstrom. The invention provides a new sequence of steps for the formation of gate spacers.
The invention addresses the above-indicated problems of white pixel formation while at the same time providing a good method for endpoint detection during the etching of the gate spacers. The invention further prevents the occurrence of plasma damage to the surface of the substrate thereby reducing leakage current along the surface of the substrate.
U.S. Pat. No. 5,899,722 (Huang) discloses a process using a double spacer.
U.S. Pat. No. 5,863,824 (Gardner) shows a two step spacer process that protects the substrate surface during the etch.
U.S. Pat. No. 5,811,342 (Wu) shows a sloping spacer 22 process for a graded LDD. However, this reference differs from the invention.
U.S. Pat. No. 5,837,563 (Hynecek) and U.S. Pat. No. 5,385,849 (Nakashiba) show CMOS Tx image sensor processes.